Mavrick wrote:
> That's what I thought, but I was hoping that there was some sort of
> nifty, whiz-bang command line inquiry that I didn't know about that
> would say, "DDR333" or whatever. I do like how lshw will show the
> capacity. That's pretty cool. Thanks!
>
> --
> --Michael Hast (the evyl robot)
> Are monestaries cold because of all the parishables?
>
>
>
> I know that this is a Linux list but maybe someone can pipe in with
> a *nix compatible program that does the following:
>
> There is a freeware (for personal use) win32 app called Aida32 that is
> a lightweight systems diag tool that when loaded and run can tell you
> all sorts of info about the guts of your computer, including the
> make/model/type/speed of the installed memory and the RAM capacity of
> the installed mobo (among other things).
Linux has a wide assortment of things in /proc and /sysfs that let you
query the hardware in your system. There are KDE, GNOME, and other
desktop apps that will show such things on your toolbar, but I'm not an
overclocker with a need for such things.
> Again, maybe someone can lend insight on a Linux alternative that is
> not distro-specific?
It's far more useful to know _how_ and _why_. Most Windows folks seem
completely hidden from the goings on within their machines. I chalk this
up to laziness. It's all part of the schadenfreude of being forced into
supporting that environment in the first place.
Querying the speed and timings of your SDRAM DIMM memory is easy enough;
each SDRAM DIMM contains a bunch of RAM chips with a small EEPROM that
contains timing another other technical information that your systems'
BIOS can read to auto-configure your system correctly on boot. The bus
used to query such things is your system's I2C/SMBUS.
Get and build the i2c modules for your motherboard and lm_sensors. The
lm_sensors package has a "decode-dimms.pl" script that makes it human
readable.
There are many I2C/SMBUS devices you can communicate with, though it can
be a challenge to decypher the labarynth of controllers, chipsets,
tolerances/thresholds, and vendor information needed to accurately model
the hardware in your system. Every motherboard iteration (even of the
same model line from the same vendor) seems to fiddling with chipsets
enough to make this a royal PITA.
- Ian
PS. Below is the output from decode-dimms.pl on my office workstation
(an Athlon XP 2600)
# ./decode-dimms.pl
PC DIMM Serial Presence Detect Tester/Decoder
By Philip Edelbrock, Christian Zuckschwerdt, Burkart Lingner and others
Version 2.9.2
Decoding EEPROM /sys/bus/i2c/drivers/eeprom/0-0050
Guessing DIMM is in bank 1
---=== The Following is Required Data and is Applicable to all DIMM
Types ===---
# of bytes written to SDRAM EEPROM 128
Total number of bytes in EEPROM 256
Fundamental Memory type DDR SDRAM
Number of Row Address Bits (SDRAM only) 13
Number of Col Address Bits (SDRAM only) 11
Number of Module Rows 2
Data Width (SDRAM only) 64
Module Interface Signal Levels SSTL 2.5
Cycle Time (SDRAM) highest CAS latency 5ns
Maximum module speed DDR 400MHz (PC3200)
Access Time (SDRAM) 6.5ns
Module Configuration Type No Parity
Refresh Type Self Refreshing
Refresh Rate Reduced (7.8uS)
Primary SDRAM Component Bank Config No Bank2 OR Bank2 = Bank1 width
Primary SDRAM Component Widths 8
Error Checking SDRAM Component Bank Config No Bank2 OR Bank2 =
Bank1 width
Error Checking SDRAM Component Widths Undefined!
Min Clock Delay for Back to Back Random Access 1
---=== The Following Apply to SDRAM DIMMs ONLY ===---
Burst lengths supported Burst Length = 2
Burst Length = 4
Burst Length = 8
Number of Device Banks 4
Supported CAS Latencies CAS Latency = 4
CAS Latency = 5
Supported CS Latencies CS Latency = 0
Supported WE Latencies WE Latency = 1
SDRAM Module Attributes Differential Clock Input
SDRAM Device Attributes (General) Lower VCC Tolerance:10%
Upper VCC Tolerance:10%
Undefined (bit 6)
Undefined (bit 7)
SDRAM Cycle Time (2nd highest CAS) 6nS
SDRAM Access from Clock Time (2nd highest CAS) 7nS
---=== The Following are Optional (may be Bogus) ===---
SDRAM Cycle Time (3rd highest CAS) 29.25nS
SDRAM Access from Clock Time (3rd highest CAS) 29.25nS
---=== The Following are Required (for SDRAMs) ===---
Minimum Row Precharge Time 80nS
Row Active to Row Active Min 40nS
RAS to CAS Delay 80nS
Min RAS Pulse Width 40nS
---=== The Following are Required and Apply to ALL DIMMs ===---
Row Densities 512 MByte
---=== The Following are Proposed and Apply to SDRAM DIMMs ===---
Command and Address Signal Setup Time 6nS
Command and Address Signal Hold Time 6nS
Data Signal Setup Time 4nS
Data Signal Hold Time 4nS
SPD Revision code 11
EEPROM Checksum of bytes 0-62 OK (0xD2)
Manufacturer's JEDEC ID Code 0x4341533300000000
Manufacturer's JEDEC ID Code ("CAS3")
Manufacturing Location Code 0x02
Manufacurer's Part Number
Revision Code 0x0000
Manufacturing Date 0x0452
Intel Specification for Frequency Undefined!
Intel Spec Details for 100MHz Support Junction Temp B (100 degrees C)
Single Sided DIMM
Decoding EEPROM /sys/bus/i2c/drivers/eeprom/0-0051
Guessing DIMM is in bank 2
---=== The Following is Required Data and is Applicable to all DIMM
Types ===---
# of bytes written to SDRAM EEPROM 128
Total number of bytes in EEPROM 256
Fundamental Memory type DDR SDRAM
Number of Row Address Bits (SDRAM only) 13
Number of Col Address Bits (SDRAM only) 11
Number of Module Rows 2
Data Width (SDRAM only) 64
Module Interface Signal Levels SSTL 2.5
Cycle Time (SDRAM) highest CAS latency 5ns
Maximum module speed DDR 400MHz (PC3200)
Access Time (SDRAM) 6.5ns
Module Configuration Type No Parity
Refresh Type Self Refreshing
Refresh Rate Reduced (7.8uS)
Primary SDRAM Component Bank Config No Bank2 OR Bank2 = Bank1 width
Primary SDRAM Component Widths 8
Error Checking SDRAM Component Bank Config No Bank2 OR Bank2 =
Bank1 width
Error Checking SDRAM Component Widths Undefined!
Min Clock Delay for Back to Back Random Access 1
---=== The Following Apply to SDRAM DIMMs ONLY ===---
Burst lengths supported Burst Length = 2
Burst Length = 4
Burst Length = 8
Number of Device Banks 4
Supported CAS Latencies CAS Latency = 4
CAS Latency = 5
Supported CS Latencies CS Latency = 0
Supported WE Latencies WE Latency = 1
SDRAM Module Attributes Differential Clock Input
SDRAM Device Attributes (General) Lower VCC Tolerance:10%
Upper VCC Tolerance:10%
Undefined (bit 6)
Undefined (bit 7)
SDRAM Cycle Time (2nd highest CAS) 6nS
SDRAM Access from Clock Time (2nd highest CAS) 7nS
---=== The Following are Optional (may be Bogus) ===---
SDRAM Cycle Time (3rd highest CAS) 29.25nS
SDRAM Access from Clock Time (3rd highest CAS) 29.25nS
---=== The Following are Required (for SDRAMs) ===---
Minimum Row Precharge Time 80nS
Row Active to Row Active Min 40nS
RAS to CAS Delay 80nS
Min RAS Pulse Width 40nS
---=== The Following are Required and Apply to ALL DIMMs ===---
Row Densities 512 MByte
---=== The Following are Proposed and Apply to SDRAM DIMMs ===---
Command and Address Signal Setup Time 6nS
Command and Address Signal Hold Time 6nS
Data Signal Setup Time 4nS
Data Signal Hold Time 4nS
SPD Revision code 11
EEPROM Checksum of bytes 0-62 OK (0xD2)
Manufacturer's JEDEC ID Code 0x4341533300000000
Manufacturer's JEDEC ID Code ("CAS3")
Manufacturing Location Code 0x02
Manufacurer's Part Number
Revision Code 0x0000
Manufacturing Date 0x0452
Intel Specification for Frequency Undefined!
Intel Spec Details for 100MHz Support Junction Temp B (100 degrees C)
Single Sided DIMM
Number of SDRAM DIMMs detected and decoded 2
Try './decode-dimms.pl --format' for html output.
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